Freescale Semiconductor /MKE18F16 /MCM /LMDR2

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Interpret as LMDR2

LMSZH=0, WY=0000, LMSZ=0000, MT=000, V=0, RO=0

Description

Local Memory Descriptor Register

Fields

CF0	Control Field 0
CF1	Control Field 1 - for Cache Parity control functions
MT	Memory Type 0 (000): SRAM_L 1 (001): SRAM_U 2 (010): PC Cache 3 (011): PS Cache
RO	(??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”) 0 (0): (??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”). Writes to the LMDRn[7:0] are allowed. 1 (1): (??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”). Writes to the LMDRn[7:0] are ignored.
DPW	LMEM Data Path Width. This read-only field defines the width of the local memory. 2 (010): LMEMn 32-bits wide 3 (011): LMEMn 64-bits wide
WY	Level 1 Cache Ways 0 (0000): No Cache 2 (0010): 2-Way Set Associative 4 (0100): 4-Way Set Associative
LMSZ	(??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”) 0 (0000): no LMEMn (0 KB) 1 (0001): 1 KB LMEMn 2 (0010): 2 KB LMEMn 3 (0011): 4 KB LMEMn 4 (0100): 8 KB LMEMn 5 (0101): 16 KB LMEMn 6 (0110): 32 KB LMEMn 7 (0111): 64 KB LMEMn 8 (1000): 128 KB LMEMn 9 (1001): 256 KB LMEMn 10 (1010): 512 KB LMEMn 11 (1011): 1024 KB LMEMn 12 (1100): 2048 KB LMEMn 13 (1101): 4096 KB LMEMn 14 (1110): 8192 KB LMEMn 15 (1111): 16384 KB LMEMn
LMSZH	(??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”) 0 (0): LMEMn is a power-of-2 capacity. 1 (1): LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ.
V	Local memory Valid bit. This read-only field defines the validity (presence) of the local memory. 0 (0): (??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”). LMEMn is not present. 1 (1): (??TBD?? current content from “MSCM OCMEM Configuration Register Descriptions”). LMEMn is present.

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